Samsung’s zHBM stacks DRAM directly atop AI accelerators, creating a vertical column that boosts bandwidth while shrinking footprint. The design promises up to three times the data rate of conventional HBM and reduces power per gigabyte, addressing the bottleneck that limits AI training speed for next‑gen model applications.
Unlike traditional HBM, which sits beside processors and adds latency, zHBM’s close‑integration shortens the signal path. This reduces both latency and power loss, delivering a measurable boost for matrix‑heavy AI tasks in real‑time scenarios. Early silicon tests indicate a 30‑40 % lift in training throughput without a proportional energy rise.
If mass production follows prototype success, data centers could replace bulky HBM modules with compact stacks, saving rack space and cooling costs. Edge devices for edge deployments would gain similar size and power benefits and reliability. Samsung aims for low‑volume rollout this year to hyperscale clouds, prompting rivals to accelerate their vertical‑stack strategies.
Source: Read original article